Datasheet

Bits 7:4 – BITS[3:0] Bits Per T
ransfer
(See Note under the register table in SPI Chip Select Register.)
The BITS field determines the number of data bits transferred. Reserved values should not be used.
Value Name Description
0
8_BIT 8 bits for transfer
1
9_BIT 9 bits for transfer
2
10_BIT 10 bits for transfer
3
11_BIT 11 bits for transfer
4
12_BIT 12 bits for transfer
5
13_BIT 13 bits for transfer
6
14_BIT 14 bits for transfer
7
15_BIT 15 bits for transfer
8
16_BIT 16 bits for transfer
9
– Reserved
10
– Reserved
11
– Reserved
12
– Reserved
13
– Reserved
14
– Reserved
15
– Reserved
Bit 3 – CSAAT Chip Select Active After T
ransfer
Value Description
0
The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1
The Peripheral Chip Select Line does not rise after the last transfer is achieved. It remains active until a
new transfer is requested on a dif
ferent chip select.
Bit 2 – CSNAAT Chip Select Not Active After T
ransfer (ignored if CSAAT = 1)
Value Description
0
The Peripheral Chip Select Line does not rise between two transfers if SPI_TDR is reloaded before the
end of the first transfer and if the two transfers occur on the same chip select.
1
The Peripheral Chip Select Line rises systematically after each transfer performed on the same slave.
It remains inactive after the end of transfer for a minimal duration of:
DLYBCS
f
peripheralclock
(If field DLYBCS is lower than 6, a minimum of six periods is introduced.)
Bit 1 – NCPHA Clock Phase
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured.
NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.
Value Description
0
Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1
Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
Bit 0 – CPOL Clock Polarity
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required clock/data relationship between master and slave devices.
Value Description
0
The inactive state value of SPCK is logic level zero.
1
The inactive state value of SPCK is logic level one.
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1002