Datasheet

41.8.9 SPI Chip Select Register
Name: SPI_CSRx
Offset: 0x30 + x*0x04 [x=0..3]
Reset: 0
Property: R/W
This register can only be written if the WPEN bit is cleared in the SPI W
rite Protection Mode Register.
SPI_CSRx must be written even if the user wants to use the default reset values. The BITS field is not updated with
the translated value unless the register is written.
Bit 31 30 29 28 27 26 25 24
DLYBCT[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DLYBS[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SCBR[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
BITS[3:0] CSAAT CSNAAT NCPHA CPOL
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:24 – DLYBCT[7:0] Delay Between Consecutive T
ransfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip
select. The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT = 0, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
DLYBCT = Delay Between Consecutive Transfers × f
peripheral clock
/ 32
Bits 23:16 – DLYBS[7:0] Delay Before SPCK
This field defines the delay from NPCS falling edge (activation) to the first valid SPCK transition.
When DLYBS = 0, the delay is half the SPCK clock period.
Otherwise, the following equation determines the delay:
DLYBS = Delay Before SPCK × f
peripheral clock
Bits 15:8 – SCBR[7:0] Serial Clock Bit Rate
In Master mode, the SPI Interface uses a modulus counter to derive the SPCK bit rate from the peripheral clock. The
bit rate is selected by writing a value from1 to 255 in the SCBR field. The following equation determines the SPCK bit
rate:
SCBR = f
peripheral clock
/ SPCK Bit Rate
Programming the SCBR field to 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable
results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
Note: If one of the SCBR fields in SPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as
well, if they are used to process transfers. If they are not used to transfer data, they can be set at any value.
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1001