Datasheet

19.4.1 Bus Matrix Master Configuration Registers
Name: MATRIX_MCFGx
Offset: 0x00 + x*0x04 [x=0..12]
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ULBT[2:0]
Access
R/W R/W R/W
Reset 0 0 0
Bits 2:0 – ULBT[2:0] Undefined Length Burst T
ype
Value Name Description
0
UNLTD_LENGTH Unlimited Length Burst—No predicted end of burst is generated, therefore INCR
bursts coming from this master can only be broken if the Slave Slot Cycle Limit is
reached. If the Slot Cycle Limit is not reached, the burst is normally completed by
the master
, at the latest, on the next AHB 1-Kbyte address boundary, allowing up
to 256-beat word bursts or 128-beat double-word bursts.
This value should not be used in the very particular case of a master capable of
performing back-to-back undefined length bursts on a single slave, since this could
indefinitely freeze the slave arbitration and thus prevent another master from
accessing this slave.
1
SINGLE_ACCESS Single Access—The undefined length burst is treated as a succession of single
accesses, allowing re-arbitration at each beat of the INCR burst or bursts
sequence.
2
4BEAT_BURST 4-beat Burst—The undefined length burst or bursts sequence is split into 4-beat
bursts or less, allowing re-arbitration every 4 beats.
3
8BEAT_BURST 8-beat Burst—The undefined length burst or bursts sequence is split into 8-beat
bursts or less, allowing re-arbitration every 8 beats.
4
16BEAT_BURST 16-beat Burst—The undefined length burst or bursts sequence is split into 16-beat
bursts or less, allowing re-arbitration every 16 beats.
5
32BEAT_BURST 32-beat Burst —The undefined length burst or bursts sequence is split into 32-beat
bursts or less, allowing re-arbitration every 32 beats.
6
64BEAT_BURST 64-beat Burst—The undefined length burst or bursts sequence is split into 64-beat
bursts or less, allowing re-arbitration every 64 beats.
SAM E70/S70/V70/V71 Family
Bus Matrix (MA
TRIX)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 100