Datasheet

37.6 Maximum Clock Frequencies
Table 37-6. Maximum GCLK Generator Output Frequencies
Symbol Description Conditions Max. Units
f
GCLKGEN0
/ f
GCLK_MAIN
f
GCLKGEN1
f
GCLKGEN2
f
GCLKGEN3
f
GCLKGEN4
f
GCLKGEN5
f
GCLKGEN6
f
GCLKGEN7
f
GCLKGEN8
GCLK Generator Output Frequency Undivided 96 MHz
Divided 48 MHz
Table 37-7. Maximum Peripheral Clock Frequencies
Symbol Description Max. Units
f
CPU
CPU clock frequency 48 MHz
f
AHB
AHB clock frequency 48 MHz
f
APBA
APBA clock frequency 48 MHz
f
APBB
APBB clock frequency 48 MHz
f
APBC
APBC clock frequency 48 MHz
f
GCLK_DFLL48M_REF
DFLL48M Reference clock frequency 33 KHz
f
GCLK_DPLL
FDPLL96M Reference clock frequency 2 MHz
f
GCLK_DPLL_32K
FDPLL96M 32k Reference clock frequency 32 KHz
f
GCLK_WDT
WDT input clock frequency 48 MHz
f
GCLK_RTC
RTC input clock frequency 48 MHz
f
GCLK_EIC
EIC input clock frequency 48 MHz
f
GCLK_USB
USB input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_0
EVSYS channel 0 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_1
EVSYS channel 1 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_2
EVSYS channel 2 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_3
EVSYS channel 3 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_4
EVSYS channel 4 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_5
EVSYS channel 5 input clock frequency 48 MHz
SAM D21 Family
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 985