Datasheet

35.8.6 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x06
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
SYNCRDY EMPTY UNDERRUN
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – SYNCRDY Synchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Synchronization Ready Interrupt Enable bit, which disables the
Synchronization Ready interrupt.
Value Description
0
The Synchronization Ready interrupt is disabled.
1
The Synchronization Ready interrupt is enabled.
Bit 1 – EMPTY Data Buffer Empty
This flag is cleared by writing a '1' to it or by writing new data to DATABUF.
This flag is set when data is transferred from DATABUF to DATA, and the DAC is ready to receive new
data in DATABUF, and will generate an interrupt request if INTENCLR/SET.EMPTY is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Data Buffer Empty interrupt flag.
Bit 0 – UNDERRUN Underrun
This flag is cleared by writing a '1' to it.
This flag is set when a start conversion event occurs when DATABUF is empty, and will generate an
interrupt request if INTENCLR/SET.UNDERRUN is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Underrun interrupt flag.
SAM D21 Family
DAC – Digital-to-Analog Converter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 973