Datasheet

35.8.5 Interrupt Enable Set
Name: INTENSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
SYNCRDY EMPTY UNDERRUN
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – SYNCRDY Synchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Synchronization Ready Interrupt Enable bit, which disables the
Synchronization Ready interrupt.
Value Description
0
The Synchronization Ready interrupt is disabled.
1
The Synchronization Ready interrupt is enabled.
Bit 1 – EMPTY Data Buffer Empty Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Data Buffer Empty Interrupt Enable bit, which enables the Data Buffer
Empty interrupt.
Value Description
0
The Data Buffer Empty interrupt is disabled.
1
The Data Buffer Empty interrupt is enabled.
Bit 0 – UNDERRUN Underrun Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Data Buffer Underrun Interrupt Enable bit, which enables the Data Buffer
Underrun interrupt.
Value Description
0
The Data Buffer Underrun interrupt is disabled.
1
The Data Buffer Underrun interrupt is enabled.
SAM D21 Family
DAC – Digital-to-Analog Converter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 972