Datasheet

35.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
RUNSTDBY ENABLE SWRST
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – RUNSTDBY Run in Standby
This bit is not synchronized
Value Description
0
The DAC output buffer is disabled in standby sleep mode.
1
The DAC output buffer can be enabled in standby sleep mode.
Bit 1 – ENABLE Enable DAC Controller
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRLA.ENABLE will read back immediately and the corresponding bit in
the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be
cleared when the operation is complete.
Value Description
0
The peripheral is disabled or being disabled.
1
The peripheral is enabled or being enabled.
Bit 0 – SWRST Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the DAC to their initial state, and the DAC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same
write-operation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete.
CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
Value Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
SAM D21 Family
DAC – Digital-to-Analog Converter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 967