Datasheet

35.7 Register Summary
Offset Name Bit Pos.
0x00 CTRLA 7:0 RUNSTDBY ENABLE SWRST
0x01 CTRLB 7:0 REFSEL[1:0] BDWP VPD LEFTADJ IOEN EOEN
0x02 EVCTRL 7:0 EMPTYEO STARTEI
0x03 Reserved
0x04 INTENCLR 7:0 SYNCRDY EMPTY UNDERRUN
0x05 INTENSET 7:0 SYNCRDY EMPTY UNDERRUN
0x06 INTFLAG 7:0 SYNCRDY EMPTY UNDERRUN
0x07 STATUS 7:0 SYNCBUSY
0x08 DATA
7:0 DATA[7:0]
15:8 DATA[15:8]
0x0A
...
0x0B
Reserved
0x0C DATABUF
7:0 DATABUF[7:0]
15:8 DATABUF[15:8]
35.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to 35.5.8 Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-
Synchronized" or the "Read-Synchronized" property in each individual register description. For details,
refer to 35.6.7 Synchronization.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
SAM D21 Family
DAC – Digital-to-Analog Converter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 966