Datasheet

35.6.2.3 Enabling the Output Buffer
To enable the DAC output on the V
OUT
pin, the output driver must be enabled by writing a one to the
External Output Enable bit in the Control B register (CTRLB.EOEN).
The DAC output buffer provides a high-drive-strength output, and is capable of driving both resistive and
capacitive loads. To minimize power consumption, the output buffer should be enabled only when
external output is needed.
35.6.2.4 Digital to Analog Conversion
The DAC converts a digital value (stored in the DATA register) into an analog voltage. The conversion
range is between GND and the selected DAC voltage reference. The default voltage reference is the
internal reference voltage. Other voltage reference options are the analog supply voltage (VDDANA) and
the external voltage reference (VREFA). The voltage reference is selected by writing to the Reference
Selection bits in the Control B register (CTRLB.REFSEL).
The output voltage from the DAC can be calculated using the following formula:

OUT
=
DATA
03FF
 VREF
A new conversion starts as soon as a new value is loaded into DATA. DATA can either be loaded via the
APB bus during a CPU write operation, using DMA, or from the DATABUF register when a START event
occurs. Refer to 35.6.5 Events for details. As there is no automatic indication that a conversion is done,
the sampling period must be greater than or equal to the specified conversion time.
35.6.3 DMA Operation
The DAC generates the following DMA request:
• Data Buffer Empty (EMPTY): The request is set when data is transferred from DATABUF to the
internal data buffer of DAC. The request is cleared when DATABUF register is written, or by writing
a one to the EMPTY bit in the Interrupt Flag register (INTFLAG.EMPTY).
For each Start Conversion event, DATABUF is transferred into DATA and the conversion starts. When
DATABUF is empty, the DAC generates the DMA request for new data. As DATABUF is initially empty, a
DMA request is generated whenever the DAC is enabled.
If the CPU accesses the registers that are the source of a DMA request set/clear condition, the DMA
request can be lost or the DMA transfer can be corrupted, if enabled.
When DAC registers are write-protected by Peripheral Access Controller, DATABUF cannot be written. To
bypass DATABUF write protection, Bypass DATABUF Write Protection bit (CTRLB.BDWP) must be
written to '1'
35.6.4 Interrupts
The DAC Controller has the following interrupt sources:
• Data Buffer Empty (EMPTY): Indicates that the internal data buffer of the DAC is empty.
• Underrun (UNDERRUN): Indicates that the internal data buffer of the DAC is empty and a DAC
start of conversion event occurred. Refer to 35.6.5 Events for details.
• Synchronization Ready (SYNCRDY): this asynchronous interrupt can be used to wake-up the
device from any sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be
individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register
SAM D21 Family
DAC – Digital-to-Analog Converter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 963