Datasheet

Related Links
23. PORT - I/O Pin Controller
35.5.2 Power Management
The DAC will continue to operate in any Sleep mode where the selected source clock is running.
The DAC interrupts can be used to wake up the device from sleep modes.
Events connected to the event system can trigger other operations in the system without exiting sleep
modes.
Related Links
16. PM – Power Manager
35.5.3 Clocks
The DAC bus clock (CLK_DAC_APB) can be enabled and disabled by the Power Manager, and the
default state of CLK_DAC_APB can be found in the Peripheral Clock Masking section.
A generic clock (GCLK_DAC) is required to clock the DAC Controller. This clock must be configured and
enabled in the Generic Clock Controller before using the DAC Controller. Refer to GCLK – Generic Clock
Controller for details.
This generic clock is asynchronous to the bus clock (CLK_DAC_APB). Due to this asynchronicity, writes
to certain registers will require synchronization between the clock domains. Refer to 35.6.7
Synchronization for further details.
Related Links
16.6.2.6 Peripheral Clock Masking
15. GCLK - Generic Clock Controller
35.5.4 DMA
The DMA request line is connected to the DMA Controller (DMAC). Using the DAC Controller DMA
requests requires to configure the DMAC first.
Related Links
20. DMAC – Direct Memory Access Controller
35.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the DAC Controller interrupt(s)
requires the interrupt controller to be configured first.
Related Links
11.2 Nested Vector Interrupt Controller
35.5.6 Events
The events are connected to the Event System.
Related Links
24. EVSYS – Event System
35.5.7 Debug Operation
When the CPU is halted in debug mode the DAC will halt normal operation. Any on-going conversions will
be completed. The DAC can be forced to continue normal operation during debugging. If the DAC is
SAM D21 Family
DAC – Digital-to-Analog Converter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 961