Datasheet

34.8.11 Comparator Control n
Name: COMPCTRL
Offset: 0x10 + n*0x04 [n=0..1]
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
FLEN[2:0]
Access
R/W R/W R/W
Reset 0 0 0
Bit 23 22 21 20 19 18 17 16
HYST OUT[1:0]
Access
R/W R/W R/W
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
SWAP MUXPOS[1:0] MUXNEG[2:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
INTSEL[1:0] SPEED[1:0] SINGLE ENABLE
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 26:24 – FLEN[2:0] Filter Length
These bits configure the filtering for comparator n. COMPCTRLn.FLEN can only be written while
COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value Name Description
0x0
OFF No filtering
0x1
MAJ3 3-bit majority function (2 of 3)
0x2
MAJ5 5-bit majority function (3 of 5)
0x3-0x7
N/A Reserved
Bit 19 – HYST Hysteresis Enable
This bit indicates the hysteresis mode of comparator n. Hysteresis is available only for continuous mode
(COMPCTRLn. SINGLE=0). COMPCTRLn.HYST can be written only while COMPCTRLn.ENABLE is
zero.
This bit is not synchronized.
These bits are not synchronized.
Value Name
0
Hysteresis is disabled.
SAM D21 Family
AC – Analog Comparators
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 956