Datasheet

34.8.4 Interrupt Enable Clear

Name: INTENCLR

Offset: 0x04

Reset: 0x00

Property: PAC Write-Protection

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes

in this register will also be reflected in the Interrupt Enable Set register (INTENSET).

Bit 7 6 5 4 3 2 1 0

WINx WINx COMPx COMPx COMPx COMPx

Access

R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bits 5,4 – WINx Window x Interrupt Enable

Reading this bit returns the state of the Window x interrupt enable.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit disables the Window x interrupt.

Value Description

The Window x interrupt is disabled.

The Window x interrupt is enabled.

Bits 3,2,1,0 – COMPx Comparator x Interrupt Enable

Reading this bit returns the state of the Comparator x interrupt enable.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit disables the Comparator x interrupt.

Value Description

The Comparator x interrupt is disabled.

The Comparator x interrupt is enabled.

SAM D21 Family

AC – Analog Comparators

Datasheet Complete

DS40001882D-page 949