Datasheet

34.7 Register Summary
Offset Name Bit Pos.
0x00 CTRLA 7:0 LPMUX RUNSTDBY ENABLE SWRST
0x01 CTRLB 7:0 STARTx STARTx STARTx STARTx
0x02 EVCTRL
7:0 WINEOx WINEOx COMPEOx COMPEOx COMPEOx COMPEOx
15:8 COMPEIx COMPEIx COMPEIx COMPEIx
0x04 INTENCLR 7:0 WINx WINx COMPx COMPx COMPx COMPx
0x05 INTENSET 7:0 WINx WINx COMPx COMPx COMPx COMPx
0x06 INTFLAG 7:0 WINx WINx COMPx COMPx COMPx COMPx
0x07 Reserved
0x08 STATUSA 7:0 WSTATE1[1:0] WSTATE0[1:0] STATEx STATEx STATEx STATEx
0x09 STATUSB 7:0 SYNCBUSY READYx READYx READYx READYx
0x0A STATUSC 7:0 WSTATE1[1:0] WSTATE0[1:0] STATEx STATEx STATEx STATEx
0x0B Reserved
0x0C WINCTRL 7:0 WINTSEL1[1:0] WEN1 WINTSEL0[1:0] WEN0
0x0D
...
0x0F
Reserved
0x10 COMPCTRL0
7:0 INTSEL[1:0] SPEED[1:0] SINGLE ENABLE
15:8 SWAP MUXPOS[1:0] MUXNEG[2:0]
23:16 HYST OUT[1:0]
31:24 FLEN[2:0]
0x14 COMPCTRL1
7:0 INTSEL[1:0] SPEED[1:0] SINGLE ENABLE
15:8 SWAP MUXPOS[1:0] MUXNEG[2:0]
23:16 HYST OUT[1:0]
31:24 FLEN[2:0]
0x18
...
0x1F
Reserved
0x20 SCALER0 7:0 VALUE[5:0]
0x21 SCALER1 7:0 VALUE[5:0]
34.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-
Synchronized" or the "Read-Synchronized" property in each individual register description. For details,
refer to Synchronization.
SAM D21 Family
AC – Analog Comparators
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 943