Datasheet

then disabled again automatically, unless configured to wake the system from sleep. Filtering is allowed

with this configuration.

Figure 34-11. Single-Shot SleepWalking

GCLK_AC

Comparator

Output or Event

Input Event

STARTUP

34.6.15 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers

need to be synchronized when written or read.

The following bits are synchronized when written:

• Software Reset bit in control register (CTRLA.SWRST)

• Enable bit in control register (CTRLA.ENABLE)

• Enable bit in Comparator Control register (COMPCTRLn.ENABLE)

The following registers are synchronized when written:

• Window Control register (WINCTRL)

Required write-synchronization is denoted by the "Write-Synchronized" property in the register

description.