Datasheet

34.4 Signal Description
Signal Description Type
AIN[7..0] Analog input Comparator inputs
CMP[2..0] Digital output Comparator outputs
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
34.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
34.5.1 I/O Lines
Using the AC’s I/O lines requires the I/O pins to be configured. Refer to PORT - I/O Pin Controller for
details.
Related Links
23. PORT - I/O Pin Controller
34.5.2 Power Management
The AC will continue to operate in any sleep mode where the selected source clock is running. The AC’s
interrupts can be used to wake up the device from sleep modes. Events connected to the event system
can trigger other operations in the system without exiting sleep modes.
Related Links
16. PM – Power Manager
34.5.3 Clocks
The AC bus clock (CLK_AC_APB) can be enabled and disabled in the Main Clock module, MCLK (see
MCLK - Main Clock, and the default state of CLK_AC_APB can be found in Peripheral Clock Masking.
Two generic clocks (GCLK_AC_DIG and GCLK_AC_ANA) are used by the AC. The digital clock
(GCLK_AC_DIG) is required to provide the sampling rate for the comparators, while the analog clock
(GCLK_AC_ANA) is required for low voltage operation (VDDANA < 2.5V) to ensure that the resistance of
the analog input multiplexors remains low. These clocks must be configured and enabled in the Generic
Clock Controller before using the peripheral.
This generic clock is asynchronous to the bus clock (CLK_AC_APB). Due to this asynchronicity, writes to
certain registers will require synchronization between the clock domains. Refer to 34.6.15
Synchronization for further details.
Related Links
16. PM – Power Manager
34.5.4 DMA
Not applicable.
SAM D21 Family
AC – Analog Comparators
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 932