Datasheet

Value Description
1
Enable the digital result correction. The ADC conversion result in the RESULT register is
then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL
registers. Conversion time will be increased by X cycles according to the value in the Offset
Correction Value bit group in the Offset Correction register.
Bit 2 – FREERUN Free Running Mode
Value Description
0
The ADC run is single conversion mode.
1
The ADC is in free running mode and a new conversion will be initiated when a previous
conversion completes.
Bit 1 – LEFTADJ Left-Adjusted Result
Value Description
0
The ADC conversion result is right-adjusted in the RESULT register.
1
The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-
bit result will be present in the upper part of the result register. Writing this bit to zero
(default) will right-adjust the value in the RESULT register.
Bit 0 – DIFFMODE Differential Mode
Value Description
0
The ADC is running in singled-ended mode.
1
The ADC is running in differential mode. In this mode, the voltage difference between the
MUXPOS and MUXNEG inputs will be converted by the ADC.
SAM D21 Family
ADC – Analog-to-Digital Converter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 911