Datasheet

33.8.5 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
PRESCALER[2:0]
Access
R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
RESSEL[1:0] CORREN FREERUN LEFTADJ DIFFMODE
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 10:8 – PRESCALER[2:0] Prescaler Configuration
These bits define the ADC clock relative to the peripheral clock.
PRESCALER[2:0] Name Description
0x0 DIV4 Peripheral clock divided by 4
0x1 DIV8 Peripheral clock divided by 8
0x2 DIV16 Peripheral clock divided by 16
0x3 DIV32 Peripheral clock divided by 32
0x4 DIV64 Peripheral clock divided by 64
0x5 DIV128 Peripheral clock divided by 128
0x6 DIV256 Peripheral clock divided by 256
0x7 DIV512 Peripheral clock divided by 512
Bits 5:4 – RESSEL[1:0] Conversion Result Resolution
These bits define whether the ADC completes the conversion at 12-, 10- or 8-bit result resolution.
RESSEL[1:0] Name Description
0x0 12BIT 12-bit result
0x1 16BIT For averaging mode output
0x2 10BIT 10-bit result
0x3 8BIT 8-bit result
Bit 3 – CORREN Digital Correction Logic Enabled
Value Description
0
Disable the digital result correction.
SAM D21 Family
ADC – Analog-to-Digital Converter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 910