Datasheet

that e.g. in 8-bit mode, only the eight lower bits will be considered. In addition, in differential mode, the

eighth bit will be considered as the sign bit, even if the ninth bit is zero.

The INTFLAG.WINMON interrupt flag will be set if the conversion result matches the window monitor

condition.

33.6.10 Offset and Gain Correction

Inherent gain and offset errors affect the absolute accuracy of the ADC.

The offset error is defined as the deviation of the actual ADC transfer function from an ideal straight line

at zero input voltage. The offset error cancellation is handled by the Offset Correction register

(OFFSETCORR). The offset correction value is subtracted from the converted data before writing the

Result register (RESULT).

The gain error is defined as the deviation of the last output step’s midpoint from the ideal straight line,

after compensating for offset error. The gain error cancellation is handled by the Gain Correction register

(GAINCORR).

To correct these two errors, the Digital Correction Logic Enabled bit in the Control B register

(CTRLB.CORREN) must be set to ''.

Offset and gain error compensation results are both calculated according to:

Result = Conversionvalue+  OFFSETCORR  GAINCORR

The correction will introduce a latency of 13 CLK_ADC clock cycles. In free running mode this latency is

introduced on the first conversion only, since its duration is always less than the propagation delay. In

single conversion mode this latency is introduced for each conversion.

Figure 33-8. ADC Timing Correction Enabled

START

CONV0 CONV1 CONV2 CONV3

CORR0 CORR1 CORR2 CORR3

33.6.11 DMA Operation

The ADC generates the following DMA request:

• Result Conversion Ready (RESRDY): the request is set when a conversion result is available and

cleared when the RESULT register is read. When the averaging operation is enabled, the DMA

request is set when the averaging is completed and result is available.

33.6.12 Interrupts

The ADC has the following interrupt sources:

• Result Conversion Ready: RESRDY

SAM D21 Family

ADC – Analog-to-Digital Converter

Datasheet Complete

DS40001882D-page 901