Datasheet

Figure 33-4. ADC Timing for One Conversion in Differential Mode without Gain, but with Increased
Sampling Time
1 2 3 4 5 6 7 8
CLK_ADC
START
SAMPLE
INT
Converting Bit
MSB 10 9 8 7 6 5 4 3 2 1 LS B
9 10 11
Figure 33-5. ADC Timing for Free Running in Differential Mode without Gain
1
2 3 4 5 6 7 8
CLK_ADC
START
SAMPLE
INT
Converting Bit
9 10 11 12 13 14 15 16
11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5
Figure 33-6. ADC Timing for One Conversion in Single-Ended Mode without Gain
1 2 3 4 5 6 7 8
CLK_ADC
START
SAMPLE
INT
Converting Bit
9 10 11
AMPLIFY
MSB 10 9 8 7 6 5 4 3 2 1 LSB
Figure 33-7. ADC Timing for Free Running in Single-Ended Mode without Gain
1
2 3 4 5 6 7 8
CLK_ADC
START
SAMPLE
INT
Converting Bit
9 10 11 12 13 14 15 16
11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 11 10
AMPLIFY
SAM D21 Family
ADC – Analog-to-Digital Converter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 898