Datasheet

– Four bits for reference selection
• Event-triggered conversion for accurate timing (one event input)
• Optional DMA transfer of conversion result
• Hardware gain and offset compensation
• Averaging and oversampling with decimation to support, up to 16-bit result
• Selectable sampling time
33.3 Block Diagram
Figure 33-1. ADC Block Diagram
ADC
ADC0
ADCn
...
INT.SIG
ADC0
ADCn
INT.SIG
...
REFCTRL
INT1V
INTVCC
VREFB
OFFSETCORR
GAINCORRSWTRIG
EVCTRL
AVGCTRL
WINCTRL
SAMPCTRL WINUT
POST
PROCESSING
PRESCALER
CTRLA
WINLT
VREFA
CTRLB
RESULT
INPUTCTRL
33.4 Signal Description
Signal Name Type Description
VREFA Analog input External reference voltage A
VREFB Analog input External reference voltage B
ADC[19..0]
(1)
Analog input Analog input channels
Note: Refer to Configuration Summary for details on exact number of analog input channels.
SAM D21 Family
ADC – Analog-to-Digital Converter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 892