Datasheet

32.8.6.8 Host Interrupt Pipe Set Register
Name: PINTENSET
Offset: 0x109 + (n x 0x20)
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register.
This register is cleared by USB reset or when PEN[n] is zero.
Bit 7 6 5 4 3 2 1 0
STALL TXSTP PERR TRFAIL TRCPT
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 2
Bit 5 – STALL Stall Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Stall interrupt.
Value Description
0
The Stall interrupt is disabled.
1
The Stall interrupt is enabled.
Bit 4 – TXSTP Transmitted Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmitted Setup interrupt.
Value Description
0
The Transmitted Setup interrupt is disabled.
1
The Transmitted Setup interrupt is enabled.
Bit 3 – PERR Pipe Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Pipe Error interrupt.
Value Description
0
The Pipe Error interrupt is disabled.
1
The Pipe Error interrupt is enabled.
Bit 2 – TRFAIL Transfer Fail Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value Description
0
The Transfer Fail interrupt is disabled.
1
The Transfer Fail interrupt is enabled.
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 880