Datasheet

32.8.5.7 Host Interrupt Enable Register Set
Name: INTENSET
Offset: 0x18
Reset: 0x0000
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 15 14 13 12 11 10 9 8
DDISC DCONN
Access
R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
RAMACER UPRSM DNRSM WAKEUP RST HSOF
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 9 – DDISC Device Disconnection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Disconnection interrupt bit and enable the DDSIC interrupt.
Value Description
0
The Device Disconnection interrupt is disabled.
1
The Device Disconnection interrupt is enabled.
Bit 8 – DCONN Device Connection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Connection interrupt bit and enable the DCONN interrupt.
Value Description
0
The Device Connection interrupt is disabled.
1
The Device Connection interrupt is enabled.
Bit 7 – RAMACER RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access interrupt bit and enable the RAMACER interrupt.
Value Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled.
Bit 6 – UPRSM Upstream Resume from the device Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume interrupt bit and enable the UPRSM interrupt.
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 864