Datasheet

32.8.5.6 Host Interrupt Enable Register Clear
Name: INTENCLR
Offset: 0x14
Reset: 0x0000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 15 14 13 12 11 10 9 8
DDISC DCONN
Access
R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
RAMACER UPRSM DNRSM WAKEUP RST HSOF
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 9 – DDISC Device Disconnection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Disconnection interrupt Enable bit and disable the
corresponding interrupt request.
Value Description
0
The Device Disconnection interrupt is disabled.
1
The Device Disconnection interrupt is enabled and an interrupt request will be generated
when the Device Disconnection interrupt Flag is set.
Bit 8 – DCONN Device Connection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Connection interrupt Enable bit and disable the
corresponding interrupt request.
Value Description
0
The Device Connection interrupt is disabled.
1
The Device Connection interrupt is enabled and an interrupt request will be generated when
the Device Connection interrupt Flag is set.
Bit 7 – RAMACER RAM Access Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding
interrupt request.
Value Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled and an interrupt request will be generated when the
RAM Access interrupt Flag is set.
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 862