Datasheet

32.8.5.2 Host Start-of-Frame Control
Name: HSOFC
Offset: 0x0A
Reset: 0x00
Property: PAC Write-Protection
During a very short period just before transmitting a Start-of-Frame, this register is locked. Thus, after
writing, it is recommended to check the register value, and write this register again if necessary. This
register is cleared upon a USB reset.
Bit 7 6 5 4 3 2 1 0
FLENCE FLENC[3:0]
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 – FLENCE Frame Length Control Enable
When this bit is '1', the time between Start-of-Frames can be tuned by up to +/-0.06% using FLENC[3:0].
Note: In Low Speed mode, FLENCE must be '0'.
Value Description
0
Start-of-Frame is generated every 1ms.
1
Start-of-Frame generation depends on the signed value of FLENC[3:0].
USB Start-of-Frame period equals 1ms + (FLENC[3:0]/12000)ms
Bits 3:0 – FLENC[3:0] Frame Length Control
These bits define the signed value of the 4-bit FLENC that is added to the Internal Frame Length when
FLENCE is '1'. The internal Frame length is the top value of the frame counter when FLENCE is zero.
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 858