Datasheet

32.8.3.7 Device Interrupt EndPoint Set n
Name: EPINTENSETn
Offset: 0x109 + (n x 0x20)
Reset: 0x0000
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENCLR) register. This
register is cleared by USB reset or when EPEN[n] is zero.
Bit 7 6 5 4 3 2 1 0
STALL RXSTP TRFAIL TRCPT
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 5 – STALL Transmit Stall x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmit bank x Stall interrupt.
Value Description
0
The Transmit Stall x interrupt is disabled.
1
The Transmit Stall x interrupt is enabled.
Bit 4 – RXSTP Received Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Received Setup interrupt.
Value Description
0
The Received Setup interrupt is disabled.
1
The Received Setup interrupt is enabled.
Bit 2 – TRFAIL Transfer Fail bank x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value Description
0
The Transfer Fail interrupt is disabled.
1
The Transfer Fail interrupt is enabled.
Bit 0 – TRCPT Transfer Complete bank x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete x interrupt.
0.2.4 Device Registers - Endpoint RAM
Value Description
0
The Transfer Complete bank x interrupt is disabled.
1
The Transfer Complete bank x interrupt is enabled.
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 849