Datasheet

32.8.3.6 Device EndPoint Interrupt Enable n
Name: EPINTENCLRn
Offset: 0x108 + (n x 0x20)
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENSET) register.
Bit 7 6 5 4 3 2 1 0
STALL RXSTP TRFAIL TRCPT
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 5 – STALL Transmit STALL x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Stall x Interrupt Enable bit and disable the corresponding
interrupt request.
Value Description
0
The Transmit Stall x interrupt is disabled.
1
The Transmit Stall x interrupt is enabled and an interrupt request will be generated when the
Transmit Stall x Interrupt Flag is set.
Bit 4 – RXSTP Received Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Setup Interrupt Enable bit and disable the corresponding
interrupt request.
Value Description
0
The Received Setup interrupt is disabled.
1
The Received Setup interrupt is enabled and an interrupt request will be generated when the
Received Setup Interrupt Flag is set.
Bit 2 – TRFAIL Transfer Fail x Interrupt Enable
The user should look into the descriptor table status located in ram to be informed about the error
condition : ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail x Interrupt Enable bit and disable the corresponding
interrupt request.
Value Description
0
The Transfer Fail bank x interrupt is disabled.
1
The Transfer Fail bank x interrupt is enabled and an interrupt request will be generated when
the Transfer Fail x Interrupt Flag is set.
Bit 0 – TRCPT Transfer Complete x interrupt Enable
Writing a zero to this bit has no effect.
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 847