Datasheet

32.8.2.5 Device Interrupt Enable Clear
Name:  INTENCLR
Offset:  0x14
Reset:  0x0000
Property:  PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 15 14 13 12 11 10 9 8
LPMSUSP LPMNYET
Access
R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 9 – LPMSUSP Link Power Management Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Suspend Interrupt Enable bit and disable
the corresponding interrupt request.
Value Description
0
The Link Power Management Suspend interrupt is disabled.
1
The Link Power Management Suspend interrupt is enabled and an interrupt request will be
generated when the Link Power Management Suspend interrupt Flag is set.
Bit 8 – LPMNYET Link Power Management Not Yet Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Not Yet interrupt Enable bit and disable the
corresponding interrupt request.
Value Description
0
The Link Power Management Not Yet interrupt is disabled.
1
The Link Power Management Not Yet interrupt is enabled and an interrupt request will be
generated when the Link Power Management Not Yet interrupt Flag is set.
Bit 7 – RAMACER RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding
interrupt request.
Value Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled and an interrupt request will be generated when the
RAM Access interrupt Flag is set.
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 831