Datasheet

32.8.1.2 Synchronization Busy

Name: SYNCBUSY

Offset: 0x02

Reset: 0x00

Property: -

Bit 7 6 5 4 3 2 1 0

ENABLE SWRST

Access

R R

Reset 0 0

Bit 1 – ENABLE Synchronization Enable status bit

This bit is cleared when the synchronization of ENABLE register between the clock domains is complete.

This bit is set when the synchronization of ENABLE register between clock domains is started.

Bit 0 – SWRST Synchronization Software Reset status bit

This bit is cleared when the synchronization of SWRST register between the clock domains is complete.

This bit is set when the synchronization of SWRST register between clock domains is started.

SAM D21 Family

USB – Universal Serial Bus

Datasheet Complete

DS40001882D-page 821