Datasheet

The user can follow the current bank looking at Current Bank bit in PSTATUS (PSTATUS.CURBK) and by
looking at Data Toggle for IN pipe bit in PSTATUS (PSTATUS.DTGLIN).
When the pipe is configured as single bank (Pipe Bank bit in PCFG (PCFG.BK) is 0), only
PINTFLAG.TRCPT0 and PSTATUS.BK0 are used. When the pipe is configured as dual bank (PCFG.BK
is 1), both PINTFLAG.TRCPT0/1 and PSTATUS.BK0/1 are used.
32.6.3.11 Management of OUT Pipes
OUT packets are sent by the host. All the data stored in the bank will be sent to the device provided the
bank is filled. The pipe and its descriptor in RAM must be configured.
The host can send data to the device by writing to the data bank 0 in single bank or the data bank 0/1 in
dual bank.
The generation of OUT packet starts when the pipe is unfrozen (PSTATUS.PFREEZE is zero).
The user writes the OUT data to the data buffer pointer by ADDR in the pipe descriptor and allows the
USB to send the data by writing a one to the PSTATUS.BK0/1RDY. This will also cause a switch to the
next bank if the OUT pipe is part of a dual bank configuration.
PINTFLAGn.TRCPT0/1 must be cleared before setting PSTATUS.BK0/1RDY to avoid missing an
PINTFLAGn.TRCPT0/1 event.
32.6.3.12 Alternate Pipe
The user has the possibility to run sequentially several logical pipes on the same physical pipe. It allows
addressing of any device endpoint of any attached device on the bus.
Before switching pipe, the user should save the pipe context (Pipe registers and descriptor for pipe n).
After switching pipe, the user should restore the pipe context (Pipe registers and descriptor for pipe n)
and in particular PCFG, and PSTATUS.
32.6.3.13 Data Flow Error
This error exists only for isochronous and interrupt pipes for both IN and OUT directions. It sets the
Transmit Fail bit in PINTFLAG (PINTFLAG.TRFAIL), which triggers an interrupt if the Transmit Fail bit in
PINTENCLR/SET(PINTENCLR/SET.TRFAIL) is set. The user must check the Pipe Interrupt Summary
register (PINTSMRY) to find out the pipe which triggered the interrupt. Then the user must check the
origin of the interrupt’s bank by looking at the Pipe Bank Status register (STATUS_BK) for each bank. If
the Error Flow bit in the STATUS_BK (STATUS_BK.ERRORFLOW) is set then the user is able to
determine the origin of the data flow error. As the user knows that the endpoint is an IN or OUT the error
flow can be deduced as OUT underflow or as an IN overflow.
An underflow can occur during an OUT stage if the host attempts to send data from an empty bank. If a
new transaction is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
An overflow can occur during an IN stage if the device tries to send a packet while the bank is full.
Typically this occurs when a CPU is not fast enough. The packet data is not written to the bank and is
lost. If a new transaction is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be
cleared.
32.6.3.14 CRC Error
This error exists only for isochronous IN pipes. It sets the PINTFLAG.TRFAIL, which triggers an interrupt
if PINTENCLR/SET.TRFAIL is set. The user must check the PINTSMRY to find out the pipe which
triggered the interrupt. Then the user must check the origin of the interrupt’s bank by looking at the bank
descriptor STATUS_BK for each bank and if the CRC Error bit in STATUS_BK (STATUS_BK.CRCERR) is
set then the user is able to determine the origin of the CRC error. A CRC error can occur during the IN
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 810