Datasheet

known values before using the pipe, so that the USB controller does not read the random values from the
RAM.
The Pipe Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size
reported by the device for the endpoint associated with this pipe. The Address of Data Buffer register
(ADDR) should be set to the data buffer used for pipe transfers.
The Pipe Bank bit (PCFG.BK) should be set to one if dual banking is desired. Dual bank is not supported
for Control pipes.
The Ram Access Interrupt bit in Host Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM
access underflow error occurs during an OUT stage.
When a pipe is disabled, the following registers are cleared for that pipe:
• Interval for the Bulk-Out/Ping transaction register (BINTERVAL)
• Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
• Pipe Interrupt Flag register (PINTFLAG)
• Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
32.6.3.5 Pipe Activation
A disabled pipe is inactive, and will be reset along with its context registers (pipe registers for the pipe n).
Pipes are enabled by writing the Type of the Pipe bit (PCFG.PTYPE) to a value different than 0x0
(disabled).
When a pipe is enabled, the Pipe Freeze bit in the Pipe Status register (PSTATUS.FREEZE) is set. This
allows the user to complete the configuration of the pipe, without starting a USB transfer.
When starting an enumeration, the user retrieves the device descriptor by sending a GET_DESCRIPTOR
USB request. This descriptor contains the maximal packet size of the device default control endpoint
(bMaxPacketSize0), which the user should use to reconfigure the size of the default control pipe.
32.6.3.6 Pipe Address Setup
Once the device has answered the first host requests with the default device address 0, the host assigns
a new address to the device. The host controller has to send a USB reset to the device and a
SET_ADDRESS(addr) SETUP request with the new address to be used by the device. Once this SETUP
transaction is complete, the user writes the new address to the Pipe Device Address field in the Host
Control Pipe register (CTRL_PIPE.PDADDR) in Pipe descriptor. All following requests by this pipe will be
performed using this new address.
32.6.3.7 Suspend and Wakeup
Setting CTRLB.SOFE to zero when in host mode will cause the USB to cease sending Start-of-Frames
on the USB bus and enter the Suspend state. The USB device will enter the Suspend state 3ms later.
Before entering suspend by writing CTRLB.SOFE to zero, the user must freeze the active pipes by
setting their PSTATUS.FREEZE bit. Any current on-going pipe will complete its transaction, and then all
pipes will be inactive. The user should wait at least 1 complete frame before entering the suspend mode
to avoid any data loss.
The device can awaken the host by sending an Upstream Resume (Remote Wakeup feature). When the
host detects a non-idle state on the USB bus, it sets the INTFLAG.WAKEUP. If the non-idle bus state
corresponds to an Upstream Resume (K state), the Upstream Resume Received Interrupt bit in INTFLAG
(INTFLAG.UPRSM) is set and the user must generate a Downstream Resume within 1 ms and for at
least 20 ms. It is required to first write a one to the Send USB Resume bit in CTRLB (CTRLB.RESUME)
to respond to the upstream resume with a downstream resume. Alternatively, the host can resume from a
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 808