Datasheet

32.6.3 Host Operations
This section gives an overview of the USB module Host operation during normal transactions. For more
details on general USB and USB protocol, refer to Universal Serial Bus Specification revision 2.1.
32.6.3.1 Device Detection and Disconnection
Prior to device detection the software must set the VBUS is OK bit (CTRLB.VBUSOK) register when the
VBUS is available. This notifies the USB host that USB operations can be started. When the bit
CTRLB.VBUSOK is zero and even if the USB HOST is configured and enabled, host operation is halted.
Setting the bit CTRLB.VBUSOK will allow host operation when the USB is configured.
The Device detection is managed by the software using the Line State field in the Host Status
(STATUS.LINESTATE) register. The device connection is detected by the host controller when DP or DM
is pulled high, depending of the speed of the device.
The device disconnection is detected by the host controller when both DP and DM are pulled down using
the STATUS.LINESTATE registers.
The Device Connection Interrupt bit (INTFLAG.DCONN) is set if a device connection is detected.
The Device Disconnection Interrupt bit (INTFLAG.DDISC) is set if a device disconnection is detected.
32.6.3.2 Host Terminology
In host mode, the term pipe is used instead of endpoint. A host pipe corresponds to a device endpoint,
refer to "Universal Serial Bus Specification revision 2.1." for more information.
32.6.3.3 USB Reset
The USB sends a USB reset signal when the user writes a one to the USB Reset bit
(CTRLB.BUSRESET). When the USB reset has been sent, the USB Reset Sent Interrupt bit in the
INTFLAG (INTFLAG.RST) is set and all pipes will be disabled.
If the bus was previously in a suspended state (i.e., the Start of Frame Generation Enable bit
(CTRLB.SOFE) is zero), the USB will switch it to the Resume state, causing the bus to asynchronously
set the Host Wakeup Interrupt flag (INTFLAG.WAKEUP). The CTRLB.SOFE bit will be set in order to
generate SOFs immediately after the USB reset.
During USB reset the following registers are cleared:
• All Host Pipe Configuration register (PCFG)
• Host Frame Number register (FNUM)
• Interval for the Bulk-Out/Ping transaction register (BINTERVAL)
• Host Start-of-Frame Control register (HSOFC)
• Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
• Pipe Interrupt Flag register (PINTFLAG)
• Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
After the reset the user should check the Speed Status field in the Status register (STATUS.SPEED) to
find out the current speed according to the capability of the peripheral.
32.6.3.4 Pipe Configuration
Pipe data can be placed anywhere in the RAM. The USB controller accesses these pipes directly through
the AHB master (built-in DMA) with the help of the pipe descriptors. The base address of the pipe
descriptors needs to be written in the Descriptor Address register (DESCADD) by the user. Refer also to
32.8.7.1 Pipe Descriptor Structure.
Before using a pipe, the user should configure the direction and type of the pipe in Type of Pipe field in
the Host Pipe Configuration register (PCFG.PTYPE). The pipe descriptor registers should be initialized to
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 807