Datasheet

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AMOD[1:0] Short name External range restrictions

1 EEPROM CRC32 of the whole EEPROM emulation area DATA forced to 0xFFFFFFFF

before calculation (no seed)

2-3 Reserved

The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial

0xEDB88320 (reversed representation).

13.11.3.1 Starting CRC32 Calculation

CRC32 calculation for a memory range is started after writing the start address into the Address register

(ADDR) and the size of the memory range into the Length register (LENGTH). Both must be word-

aligned.

The initial value used for the CRC32 calculation must be written to the Data register (DATA). This value

will usually be 0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if

generating a common CRC32 of separate memory blocks.

Once completed, the calculated CRC32 value can be read out of the Data register. The read value must

be complemented to match standard CRC32 implementations or kept non-inverted if used as starting

point for subsequent CRC32 calculations.

The actual test is started by writing a '1' in the 32-bit Cyclic Redundancy Check bit of the Control register

(CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing '1' to

CTRL.SWRST).

Related Links

22. NVMCTRL – Nonvolatile Memory Controller

22.6.6 Security Bit

13.11.3.2 Interpreting the Results

The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set.

Then the Bus Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus

error occurred.

13.11.4 Debug Communication Channels

The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated

handshake logic, accessible by both CPU and debugger even if the device is protected by the NVMCTRL

security bit. The registers can be used to exchange data between the CPU and the debugger, during run

time as well as in debug mode. This enables the user to build a custom debug protocol using only these

registers.

The DCC0 and DCC1 registers are accessible when the protected state is active. When the device is

protected, however, it is not possible to connect a debugger while the CPU is running

(STATUSA.CRSTEXT is not writable and the CPU is held under Reset).

Two Debug Communication Channel status bits in the Status B registers (STATUS.DCCDx) indicate

whether a new value has been written in DCC0 or DCC1. These bits, DCC0D and DCC1D, are located in

the STATUSB registers. They are automatically set on write and cleared on read.

Note: The DCC0 and DCC1 registers are shared with the on-board memory testing logic (MBIST).

Accordingly, DCC0 and DCC1 must not be used while performing MBIST operations.

SAM D21 Family

DSU - Device Service Unit

Datasheet Complete

DS40001882D-page 80