Datasheet

When the EPCFG.EPTYPE0 matches, the USB module then fetches the Data Buffer Address (ADDR)
from the addressed endpoint's descriptor and waits for a DATA0 packet. If a PID error or any other PID
than DATA0 is detected, the USB module returns to idle and waits for the next token packet.
When the data PID matches and if the Received Setup Complete interrupt bit in the Device Endpoint
Interrupt Flag register (EPINTFLAG.RXSTP) is equal to zero, ignoring the Bank 0 Ready bit in the Device
Endpoint Status register (EPSTATUS.BK0RDY), the incoming data is written to the data buffer pointed to
by the Data Buffer Address (ADDR). If the number of received data bytes exceeds the endpoint's
maximum data payload size as specified by the PCKSIZE.SIZE, the remainders of the received data
bytes are discarded. The packet will still be checked for bit-stuff and CRC errors. Software must never
report a endpoint size to the host that is greater than the value configured in PCKSIZE.SIZE. If a bit-stuff
or CRC error is detected in the packet, the USB module returns to idle and waits for the next token
packet.
If data is successfully received, an ACK handshake is returned to the host, and the number of received
data bytes, excluding the CRC, is written to the Byte Count (PCKSIZE.BYTE_COUNT). If the number of
received data bytes is the maximum data payload specified by PCKSIZE.SIZE, no CRC data is written to
the data buffer. If the number of received data bytes is the maximum data payload specified by
PCKSIZE.SIZE minus one, only the first CRC data is written to the data buffer. If the number of received
data is equal or less than the data payload specified by PCKSIZE.SIZE minus two, both CRC data bytes
are written to the data buffer.
Finally the EPSTATUS is updated. Data Toggle OUT bit (EPSTATUS.DTGLOUT), the Data Toggle IN bit
(EPSTATUS.DTGLIN), the current bank bit (EPSTATUS.CURRBK) and the Bank Ready 0 bit
(EPSTATUS.BK0RDY) are set. Bank Ready 1 bit (EPSTATUS.BK1RDY) and the Stall Bank 0/1 bit
(EPSTATUS.STALLQR0/1) are cleared on receiving the SETUP request. The RXSTP bit is set and
triggers an interrupt if the Received Setup Interrupt Enable bit is set in Endpoint Interrupt Enable Set/
Clear register (EPINTENSET/CLR.RXSTP).
32.6.2.7 Management of OUT Transactions
Figure 32-4. OUT Transfer: Data Packet Host to USB Device
Internal RAM
USB Module
USB Endpoints
Descriptor Table
DESCADD
USB I/O Registers
USB Buffers
ENDPOINT 1 DATA
ENDPOINT 2 DATA
ENDPOINT 3 DATA
D
A
T
A
0
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
BULK OUT
EPT 2
BULK OUT
EPT 3
BULK OUT
EPT 1
DP
DM
HOST
time
Memory Map
I/O Register
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 798