Datasheet

Refer to 32.6.2 USB Device Operations for the basic operation of the device mode.
Refer to 32.6.3 Host Operations for the basic operation of the host mode.
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10.3.2 NVM Software Calibration Area Mapping
32.6.2 USB Device Operations
This section gives an overview of the USB module device operation during normal transactions. For more
details on general USB and USB protocol, refer to the Universal Serial Bus specification revision 2.1.
32.6.2.1 Initialization
To attach the USB device to start the USB communications from the USB host, a zero should be written
to the Detach bit in the Device Control B register (CTRLB.DETACH). To detach the device from the USB
host, a one must be written to the CTRLB.DETACH.
After the device is attached, the host will request the USB device descriptor using the default device
address zero. On successful transmission, it will send a USB reset. After that, it sends an address to be
configured for the device. All further transactions will be directed to this device address. This address
should be configured in the Device Address field in the Device Address register (DADD.DADD) and the
Address Enable bit in DADD (DADD.ADDEN) should be written to one to accept communications directed
to this address. DADD.ADDEN is automatically cleared on receiving a USB reset.
32.6.2.2 Endpoint Configuration
Endpoint data can be placed anywhere in the device RAM. The USB controller accesses these endpoints
directly through the AHB master (built-in DMA) with the help of the endpoint descriptors. The base
address of the endpoint descriptors needs to be written in the Descriptor Address register (DESCADD) by
the user. Refer also to the Endpoint Descriptor structure in 32.8.4.1 Endpoint Descriptor Structure.
Before using an endpoint, the user should configure the direction and type of the endpoint in Type of
Endpoint field in the Device Endpoint Configuration register (EPCFG.EPTYPE0/1). The endpoint
descriptor registers should be initialized to known values before using the endpoint, so that the USB
controller does not read random values from the RAM.
The Endpoint Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size
reported to the host for that endpoint. The Address of Data Buffer register (ADDR) should be set to the
data buffer used for endpoint transfers.
The RAM Access Interrupt bit in Device Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM
access underflow error occurs during IN data stage.
When an endpoint is disabled, the following registers are cleared for that endpoint:
• Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register
• Device Endpoint Interrupt Flag (EPINTFLAG) register
• Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)
• Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)
32.6.2.3 Multi-Packet Transfers
Multi-packet transfer enables a data payload exceeding the endpoint maximum transfer size to be
transferred as multiple packets without software intervention. This reduces the number of interrupts and
software intervention required to manage higher level USB transfers. Multi-packet transfer is identical to
the IN and OUT transactions described below unless otherwise noted in this section.
SAM D21 Family
USB – Universal Serial Bus
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 796