Datasheet

Value Name Description
0x1
RAMP2A Alternative RAMP2 operation
0x2
RAMP2 RAMP2 operation
0x3
RAMP2C. This bit is only available in variant L devices. Refer
to Configuration Summary for more information.
Critical RAMP2 operation
0x4
- Reserved
Bits 2:0 – WAVEGENB[2:0] Waveform Generation Operation Buffer
These register bits are the buffer bits for WAVEGEN register bits. If double buffering is used, valid content
in these bits is copied to the corresponding WAVEGEN bits on a UPDATE condition.
Value
Name Description
Operation Top Update Waveform Output
On Match
Waveform Output
On Update
OVFIF/Event
Up Down
0x0 NFRQ Normal Frequency PER TOP/Zero Toggle Stable TOP Zero
0x1 MFRQ Match Frequency CC0 TOP/Zero Toggle Stable TOP Zero
0x2 NPWM Normal PWM PER TOP/Zero Set Clear TOP Zero
0x3 Reserved - - - - - - -
0x4 DSCRITICAL Dual-slope PWM PER Zero ~DIR Stable – Zero
0x5 DSBOTTOM Dual-slope PWM PER Zero ~DIR Stable – Zero
0x6 DSBOTH Dual-slope PWM PER TOP & Zero ~DIR Stable TOP Zero
0x7 DSTOP Dual-slope PWM PER Zero ~DIR Stable TOP –
SAM D21 Family
TCC – Timer/Counter for Control Applications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 786