Datasheet

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CTRLA.RESOLUTION Bits [23:m]

0x1 - DITH4 23:4

0x2 - DITH5 23:5

0x3 - DITH6 23:6 (depicted)

Bits 5:0 – DITHER[5:0] Dithering Cycle Number

These bits hold the number of extra cycles that are added on the PWM pulse width every 64 PWM

frames.

Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution

bits in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION Bits [n:0]

0x0 - NONE -

0x1 - DITH4 3:0

0x2 - DITH5 4:0

0x3 - DITH6 5:0 (depicted)

SAM D21 Family

TCC – Timer/Counter for Control Applications

Datasheet Complete

DS40001882D-page 783