Datasheet

31.8.16 Waveform
Name: WAVE
Offset: 0x3C
Reset: 0x00000000
Property: Write-Synchronized
Bit 31 30 29 28 27 26 25 24
SWAP3 SWAP2 SWAP1 SWAP0
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
POL3 POL2 POL1 POL0
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CICCEN3 CICCEN2 CICCEN1 CICCEN0
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CIPEREN RAMP[1:0] WAVEGEN[2:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 24, 25, 26, 27 – SWAP Swap DTI Output Pair x
Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings
will not affect the swap operation.
Bits 16, 17, 18, 19 – POL Channel Polarity x
Setting these bits enables the output polarity in single-slope and dual-slope PWM operations.
Value Name Description
0
(single-slope PWM waveform
generation)
Compare output is initialized to ~DIR and set to DIR when
TCC counter matches CCx value
1
(single-slope PWM waveform
generation)
Compare output is initialized to DIR and set to ~DIR when
TCC counter matches CCx value.
0
(dual-slope PWM waveform
generation)
Compare output is set to ~DIR when TCC counter matches
CCx value
1
(dual-slope PWM waveform
generation)
Compare output is set to DIR when TCC counter matches
CCx value.
Bits 8, 9, 10, 11 – CICCEN Circular CC Enable x
Setting this bits enables the compare circular buffer option on channel. When the bit is set, CCx register
value is copied-back into the CCx register on UPDATE condition.
SAM D21 Family
TCC – Timer/Counter for Control Applications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 778