Datasheet

31.8.15 Pattern
Name: PATT
Offset: 0x38
Reset: 0x0000
Property: Write-Synchronized
Bit 15 14 13 12 11 10 9 8
PGV0[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PGE0[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 8:15, 16:23, 24:31, 32:39, 40:47, 48:55, 56:63, 64:71 – PGV Pattern Generation Output Value
This register holds the values of pattern for each waveform output.
Bits 0:7, 8:15, 16:23, 24:31, 32:39, 40:47, 48:55, 56:63 – PGE Pattern Generation Output Enable
This register holds the enable status of pattern generation for each waveform output. A bit written to '1'
will override the corresponding SWAP output with the corresponding PGVn value.
SAM D21 Family
TCC – Timer/Counter for Control Applications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 777