Datasheet

31.8.13 Status
Name: STATUS
Offset: 0x30
Reset: 0x00000001
Property: -
Bit 31 30 29 28 27 26 25 24
CMPx CMPx CMPx CMPx
Access
R R R R
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CCBVx CCBVx CCBVx CCBVx
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
FAULTx FAULTx FAULTB FAULTA FAULT1IN FAULT0IN FAULTBIN FAULTAIN
Access
R/W R/W R/W R/W R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PERBV WAVEBV PATTBV DFS UFS IDX STOP
Access
R/W R/W R/W R/W R/W R R
Reset 0 0 0 0 0 0 1
Bits 27,26,25,24 – CMPx Channel x Compare Value
This bit reflects the channel x output compare value.
Value Description
0
Channel compare output value is 0.
1
Channel compare output value is 1.
Bits 19,18,17,16 – CCBVx Channel x Compare or Capture Buffer Valid
For a compare channel, this bit is set when a new value is written to the corresponding CCBx register.
The bit is cleared either by writing a '1' to the corresponding location when CTRLB.LUPD is set, or
automatically on an UPDATE condition.
For a capture channel, the bit is set when a valid capture value is stored in the CCBx register. The bit is
automatically cleared when the CCx register is read.
Bits 15,14 – FAULTx Non-recoverable Fault x State
This bit is set by hardware as soon as non-recoverable Fault x condition occurs.
This bit is cleared by writing a one to this bit and when the corresponding FAULTxIN status bit is low.
Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter
from BOTTOM, the timer/counter restart command must be executed before clearing the corresponding
SAM D21 Family
TCC – Timer/Counter for Control Applications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 773