Datasheet

31.8.4 Synchronization Busy
Name: SYNCBUSY
Offset: 0x08
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
CCB3 CCB2 CCB1 CCB0 PERB WAVEB PATTB
Access
R R R R R R R
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CC3 CC2 CC1 CC0
Access
R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PER WAVE PATT COUNT STATUS CTRLB ENABLE SWRST
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 19, 20, 21, 22 – CCB Compare/Capture Buffer Channel x Synchronization Busy
This bit is cleared when the synchronization of Compare/Capture Buffer Channel x register between the
clock domains is complete.
This bit is set when the synchronization of Compare/Capture Buffer Channel x register between clock
domains is started.
CCBx bit is available only for existing Compare/Capture Channels. For details on CC channels number,
refer to each TCC feature list.
Bit 18 – PERB PER Buffer Synchronization Busy
This bit is cleared when the synchronization of PERB register between the clock domains is complete.
This bit is set when the synchronization of PERB register between clock domains is started.
Bit 17 – WAVEB WAVE Buffer Synchronization Busy
This bit is cleared when the synchronization of WAVEB register between the clock domains is complete.
This bit is set when the synchronization of WAVEB register between clock domains is started.
Bit 16 – PATTB PATT Buffer Synchronization Busy
This bit is cleared when the synchronization of PATTB register between the clock domains is complete.
This bit is set when the synchronization of PATTB register between clock domains is started.
SAM D21 Family
TCC – Timer/Counter for Control Applications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 752