Datasheet

Figure 13-3. Hot-Plugging Detection Timing Diagram

SWCLK

Hot-Plugging

CPU_STATE

reset

running

RESET

The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected.

Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For

security reasons, Hot-Plugging is not available when the device is protected by the NVMCTRL security

bit.

This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be

done until POR is released. If the device is protected, Cold-Plugging is the only way to detect a debugger

probe, and so the external reset timing must be longer than the POR timing. If external reset is

deasserted before POR release, the user must retry the procedure above until it gets connected to the

device.

Related Links

22. NVMCTRL – Nonvolatile Memory Controller

22.6.6 Security Bit

13.7 Chip Erase

Chip-Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL

security bit. Therefore, all volatile memories and the Flash memory (including the EEPROM emulation

area) will be erased. The Flash auxiliary rows, including the user row, will not be erased.

When the device is protected, the debugger must first reset the device in order to be detected. This

ensures that internal registers are reset after the protected state is removed. The Chip-Erase operation is

triggered by writing a '1' to the Chip-Erase bit in the Control register (CTRL.CE). This command will be

discarded if the DSU is protected by the Peripheral Access Controller (PAC). Once issued, the module

clears volatile memories prior to erasing the Flash array. To ensure that the Chip-Erase operation is

completed, check the Done bit of the Status A register (STATUSA.DONE).

The Chip-Erase operation depends on clocks and power management features that can be altered by the

CPU. For that reason, it is recommended to issue a Chip- Erase after a Cold-Plugging procedure to

ensure that the device is in a known and safe state.

The recommended sequence is as follows:

1. Issue the Cold-Plugging procedure (refer to 13.6.3.1 Cold Plugging). The device then:

1.1. Detects the debugger probe.

1.2. Holds the CPU in reset.

2. Issue the Chip-Erase command by writing a '1' to CTRL.CE. The device then:

2.1. Clears the system volatile memories.

SAM D21 Family

DSU - Device Service Unit

Datasheet Complete

DS40001882D-page 75