Datasheet

Writing a '1' to this bit will disable the one-shot operation.

Value Description

The TCC will update the counter value on overflow/underflow condition and continue

operation.

The TCC will stop counting on the next underflow/overflow condition.

Bit 1 – LUPD Lock Update

This bit controls the update operation of the TCC buffered registers.

When CTRLB.LUPD is cleared, the hardware UPDATE registers with value from their buffered registers is

enabled.

This bit has no effect when input capture operation is enabled.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will enable the registers updates on hardware UPDATE condition.

Value Description

The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are copied into the

corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.

The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are not copied into

the corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update

condition.

Bit 0 – DIR Counter Direction

This bit is used to change the direction of the counter.

Writing a '0' to this bit has no effect

Writing a '1' to this bit will clear the bit and make the counter count up.

Value Description

The timer/counter is counting up (incrementing).

The timer/counter is counting down (decrementing).

SAM D21 Family

TCC – Timer/Counter for Control Applications

Datasheet Complete

DS40001882D-page 749