Datasheet

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Offset Name Bit Pos.
0x54
...
0x63
Reserved
0x64 PATTB
7:0 PGEB0[7:0]
15:8 PGVB0[7:0]
0x66
...
0x67
Reserved
0x68 WAVEB
7:0 CIPERENB RAMPB[1:0] WAVEGENB[2:0]
15:8 CICCENB3 CICCENB2 CICCENB1 CICCENB0
23:16 POLB3 POLB2 POLB1 POLB0
31:24 SWAPB 3 SWAPB 2 SWAPB 1 SWAPB 0
0x6C PERB
7:0 PERB[1:0] DITHERB[5:0]
15:8 PERB[9:2]
23:16 PERB[17:10]
31:24
0x70 CCB0
7:0 CCB[1:0] DITHERB[5:0]
15:8 CCB[9:2]
23:16 CCB[17:10]
31:24
0x74 CCB1
7:0 CCB[1:0] DITHERB[5:0]
15:8 CCB[9:2]
23:16 CCB[17:10]
31:24
0x78 CCB2
7:0 CCB[1:0] DITHERB[5:0]
15:8 CCB[9:2]
23:16 CCB[17:10]
31:24
0x7C CCB3
7:0 CCB[1:0] DITHERB[5:0]
15:8 CCB[9:2]
23:16 CCB[17:10]
31:24
31.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-
Protection" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
SAM D21 Family
TCC – Timer/Counter for Control Applications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 744