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the system. The debugger is detected on a RESET release event when SWCLK is low. At startup,
SWCLK is internally pulled up to avoid false detection of a debugger if the SWCLK pin is left
unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension bit of the
Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a '1' to STATUSA.CRSTEXT.
STATUSA.CRSTEXT will then be set to '0'. Writing a '0' to STATUSA.CRSTEXT has no effect. For
security reasons, it is not possible to release the CPU reset extension when the device is protected by the
NVMCTRL security bit. Trying to do so sets the Protection Error bit (PERR) of the Status A register
(STATUSA.PERR).
Figure 13-2. Typical CPU Reset Extension Set and Clear Timing Diagram
DSU CRSTEXT
Clear
SWCLK
CPU reset
extension
CPU_STATE
reset
running
RESET
Related Links
22. NVMCTRL – Nonvolatile Memory Controller
22.6.6 Security Bit
13.6.3 Debugger Probe Detection
13.6.3.1 Cold Plugging
Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when
the CPU reset extension is requested, as described above.
13.6.3.2 Hot Plugging
Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not
possible under reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is
active when a SWCLK falling edge is detected. The SWCLK pad is multiplexed with other functions and
the user must ensure that its default function is assigned to the debug system. If the SWCLK function is
changed, the Hot-Plugging feature is disabled until a power-reset or external reset occurs. Availability of
the Hot-Plugging feature can be read from the Hot-Plugging Enable bit of the Status B register
(STATUSB.HPE).
SAM D21 Family
DSU - Device Service Unit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 74