Datasheet

Figure 31-37. DMA Triggers in RAMP and RAMP2 Operation Mode and Circular Buffer Enabled
"update"
ZERO
DMA Channel i
DMA Channel j
Update ramp A
Update ramp B
N-2
N-1 N
A B
A
AB B
COUNT
Cycle
STATUS.IDX
DMA_CCx_req
DMA_OVF_req
Ramp
DMA Operation with Circular Buffer in DSBOTH Mode
When a CC channel is selected as a circular buffer, the related DMA request is not set on a compare
match detection, but on start of down-counting phase.
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of up-
counting phase with an effective DMA transfer on previous down-counting phase (DMA acknowledge).
When up-counting, all circular buffer values can be updated through a DMA channel triggered by MC
trigger. When down-counting, all circular buffer values can be updated through a second DMA channel,
triggered by the OVF DMA request.
Figure 31-38. DMA Triggers in DSBOTH Operation Mode and Circular Buffer Enabled
COUNT
Cycle
CTRLB.DIR
DMA_CCx_req
DMA_OVF_req
Old Parameter Set
New Parameter Set
"update"
ZERO
DMA Channel i
DMA Channel j
Update Rising
Update Rising
N-2
N-1
N
31.6.4.2 Interrupts
The TCC has the following interrupt sources:
• Overflow/Underflow (OVF)
• Retrigger (TRG)
SAM D21 Family
TCC – Timer/Counter for Control Applications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 738