Datasheet

Related Links
16. PM – Power Manager
13.5.3 Clocks
The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Power
Manager. Refer to PM – Power Manager
Related Links
16. PM – Power Manager
13.5.4 DMA
Not applicable.
13.5.5 Interrupts
Not applicable.
13.5.6 Events
Not applicable.
13.5.7 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
• Debug Communication Channel 0 register (DCC0)
• Debug Communication Channel 1 register (DCC1)
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
Write-protection does not apply for accesses through an external debugger.
Related Links
11.6 PAC - Peripheral Access Controller
13.5.8 Analog Connections
Not applicable.
13.6 Debug Operation
13.6.1 Principle of Operation
The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the
ARM processor debug resources:
• CPU reset extension
• Debugger probe detection
For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture
Specification.
13.6.2 CPU Reset Extension
“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset
is released. This ensures that the CPU is not executing code at startup while a debugger is connects to
SAM D21 Family
DSU - Device Service Unit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 73