Datasheet

In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform

output.

31.6.2.6 Double Buffering

The Pattern (PATT), Waveform (WAVE), Period (PER) and Compare Channels (CCx) registers are all

double buffered. Each buffer register has a buffer valid (PATTBV, WAVEBV, PERBV and CCBVx) bit in

the STATUS register, which indicates that the buffer register contains a valid value that can be copied into

the corresponding register. .

When the buffer valid flag bit in the STATUS register is '1' and the Lock Update bit in the CTRLB register

is set to '0', (writing CTRLBCLR.LUPD to '1'), double buffering is enabled: the data from buffer registers

will be copied into the corresponding register under hardware UPDATE conditions, then the buffer valid

flags bit in the STATUS register are automatically cleared by hardware.

Note: Software update command (CTRLBSET.CMD=0x3) act independently of LUPD value.

A compare register is double buffered as in the following figure.

Figure 31-9. Compare Channel Double Buffering

"APB write enable"

"data write"

UPDATE

COUNT

"match"

CCBx

CCx

Both the registers (PATT/WAVE/PER/CCx) and corresponding buffer registers (PATTB/WAVEBV/PERB/

CCBx) are available in the I/O register map, and the double buffering feature is not mandatory. The

double buffering is disabled by writing a '1' to CTRLSET.LUPD.

Note: In NFRQ, MFRQ or PWM down-counting counter mode (CTRLBSET.DIR=1), when double

buffering is enabled (CTRLBCLR.LUPD=1), PERB register is continuously copied into the PER

independently of update conditions.

Changing the Period

The counter period can be changed by writing a new Top value to the Period register (PER or CC0,

depending on the waveform generation mode), any period update on registers (PER or CCx) is effective

after the synchronization delay, whatever double buffering enabling is.

SAM D21 Family

TCC – Timer/Counter for Control Applications

Datasheet Complete

DS40001882D-page 718