Datasheet

N represents the prescaler divider used.
Note: In DSTOP, DSBOTTOM and DSBOTH operation, when TOP is lower than MAX/2, the CCx MSB
bit defines the ramp on which the CCx Match interrupt or event is generated. (Rising if CCx[MSB] = 0,
falling if CCx[MSB] = 1.)
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31.6.3.2 Circular Buffer
31.6.2.5.7 Dual-Slope Critical PWM Generation
Critical mode generation allows generation of non-aligned centered pulses. In this mode, the period time
is controlled by PER while CCx control the generated waveform output edge during up-counting and
CC(x+CC_NUM/2) control the generated waveform output edge during down-counting.
Figure 31-8. Dual-Slope Critical Pulse Width Modulation (N=CC_NUM)
COUNT
CCx
WO[x]
ZERO
TOP
MAX
"match"
"reload" update
CC(x+N/2) CCx CC(x+N/2) CCx CC(x+N/2)
31.6.2.5.8 Output Polarity
The polarity (WAVE.POLx) is available in all waveform output generation. In single-slope and dual-slope
PWM operation, it is possible to invert the pulse edge alignment individually on start or end of a PWM
cycle for each compare channels. The table below shows the waveform output set/clear conditions,
depending on the settings of timer/counter, direction, and polarity.
Table 31-3. Waveform Generation Set/Clear Conditions
Waveform Generation
operation
DIR POLx Waveform Generation Output Update
Set Clear
Single-Slope PWM 0 0 Timer/counter matches TOP Timer/counter matches CCx
1 Timer/counter matches CC Timer/counter matches TOP
1 0 Timer/counter matches CC Timer/counter matches ZERO
1 Timer/counter matches ZERO Timer/counter matches CC
Dual-Slope PWM x 0 Timer/counter matches CC
when counting up
Timer/counter matches CC
when counting down
1 Timer/counter matches CC
when counting down
Timer/counter matches CC
when counting up
SAM D21 Family
TCC – Timer/Counter for Control Applications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 717