Datasheet

31.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for
details.
Related Links
20. DMAC – Direct Memory Access Controller
31.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt
Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
31.5.6 Events
The events of this peripheral are connected to the Event System.
Related Links
24. EVSYS – Event System
31.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will halt normal operation. This peripheral can be
forced to continue operation during debugging - refer to the Debug Control (DBGCTRL) register for
details.
Refer to 31.8.8 DBGCTRL register for details.
31.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
Interrupt Flag register (INTFLAG)
Status register (STATUS)
Period and Period Buffer registers (PER, PERB)
Compare/Capture and Compare/Capture Buffer registers (CCx, CCBx)
Control Waveform register (WAVE)
Control Waveform Buffer register (WAVEB)
Pattern Generation Value and Pattern Generation Value Buffer registers (PATT, PATTB)
Note:  Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
Write-protection does not apply for accesses through an external debugger.
31.5.9 Analog Connections
Not applicable.
SAM D21 Family
TCC – Timer/Counter for Control Applications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 707