Datasheet

31.4 Signal Description
Pin Name Type Description
TCCx/WO[0] Digital output Compare channel 0 waveform output
TCCx/WO[1] Digital output Compare channel 1 waveform output
… ... ...
TCCx/WO[WO_NUM-1] Digital output Compare channel n waveform output
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
31.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
31.5.1 I/O Lines
In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller
(PORT).
Related Links
23. PORT - I/O Pin Controller
31.5.2 Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The
interrupts can wake up the device from sleep modes. Events connected to the event system can trigger
other operations in the system without exiting sleep modes.
31.5.3 Clocks
The TCC bus clocks (CLK_TCCx_APB) can be enabled and disabled in the Power Manager module. The
default state of CLK_TCCx_APB can be found in the Peripheral Clock Masking section (see the Related
Links below).
A generic clock (GCLK_TCCx) is required to clock the TCC. This clock must be configured and enabled
in the generic clock controller before using the TCC. Note that TCC0 and TCC1 share a peripheral clock
generator.
The generic clocks (GCLK_TCCx) are asynchronous to the bus clock (CLK_TCCx_APB). Due to this
asynchronicity, writing certain registers will require synchronization between the clock domains. Refer to
31.6.6 Synchronization for further details.
Related Links
15. GCLK - Generic Clock Controller
16.6.2.6 Peripheral Clock Masking
SAM D21 Family
TCC – Timer/Counter for Control Applications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 706